Nonidealities Study of a Continuous-Time Delta-Sigma Modulator Using VHDL-AMS Modelling

In this paper, a complete high-speed Continuous-Time Bandpass Delta-Sigma modulator for digital receiver applications is modeled, using VHDL-AMS. The main Continuous-Time DeltaSigma modulator’s nonidealities such as excess loop delay, clock jitter and multi-bit feedback DAC element mismatch in the modulator loop are also modeled and their effects evaluated. An accurate understanding of these non-ideal phenomena allows to estimate the limits of the modulator and hence to design more robust building-blocks.